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| author | Nathan Binkert <nate@binkert.org> | 2009-04-21 16:04:55 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2009-04-21 16:04:55 -0700 |
| commit | 4d001e43da6da2972172c352153e745238860021 (patch) | |
| tree | dfd0052a6ece6690540df06b4742e6d4d4cc2034 /src/cpu/BaseCPU.py | |
| parent | 4f7d6a881ce959663cb32f9bb70b4a6b40a456e1 (diff) | |
| parent | fcc142463d38fc1d752b2e45c24a9e1040ccfc9e (diff) | |
| download | gem5-4d001e43da6da2972172c352153e745238860021.tar.xz | |
Automated merge with ssh://m5sim.org//repo/m5
Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 3aa9b87bb..4661375ba 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -54,7 +54,7 @@ elif build_env['TARGET_ISA'] == 'mips': if build_env['FULL_SYSTEM']: from MipsInterrupts import MipsInterrupts elif build_env['TARGET_ISA'] == 'arm': - from ArmTLB import ArmDTB + from ArmTLB import ArmTLB if build_env['FULL_SYSTEM']: from ArmInterrupts import ArmInterrupts @@ -109,8 +109,8 @@ class BaseCPU(MemObject): MipsInterrupts(), "Interrupt Controller") elif build_env['TARGET_ISA'] == 'arm': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") - dtb = Param.ArmTLB(ArmDTB(), "Data TLB") - itb = Param.ArmTLB(ArmITB(), "Instruction TLB") + dtb = Param.ArmTLB(ArmTLB(), "Data TLB") + itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") if build_env['FULL_SYSTEM']: interrupts = Param.ArmInterrupts( ArmInterrupts(), "Interrupt Controller") |