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| author | Gabe Black <gblack@eecs.umich.edu> | 2008-10-12 14:01:06 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-10-12 14:01:06 -0700 |
| commit | d0a43ce2b29da1640248a756dcd07f0f28561df0 (patch) | |
| tree | fa3d8e0990b5a1d360c67d75d9d745307faaf242 /src/cpu/BaseCPU.py | |
| parent | 3a1905157eec2ed80eaf2ddb8be69cb2f509dfee (diff) | |
| download | gem5-d0a43ce2b29da1640248a756dcd07f0f28561df0.tar.xz | |
X86: Fix the ordering of special physical address ranges.
Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 51d447f0b..ef9b54f3f 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -97,7 +97,7 @@ class BaseCPU(MemObject): dtb = Param.X86DTB(X86DTB(), "Data TLB") itb = Param.X86ITB(X86ITB(), "Instruction TLB") if build_env['FULL_SYSTEM']: - _localApic = X86LocalApic(pio_addr=0xa000000000000000) + _localApic = X86LocalApic(pio_addr=0x2000000000000000) interrupts = \ Param.X86LocalApic(_localApic, "Interrupt Controller") elif build_env['TARGET_ISA'] == 'mips': |