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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-10-13 02:22:23 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-10-13 02:22:23 -0700 |
| commit | 8adc6781bf5741cca9a27e9e2c523b4def5a3bc3 (patch) | |
| tree | 4beebe8b1f71fe8847045bd6e57182c6ab4e1ec8 /src/cpu/BaseCPU.py | |
| parent | 4b2e5ebeada762e88ad97397b8db3ebf4658b70f (diff) | |
| download | gem5-8adc6781bf5741cca9a27e9e2c523b4def5a3bc3.tar.xz | |
X86: Turn on the page table walker in SE mode.
Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 6640f3cea..430356004 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -140,7 +140,8 @@ class BaseCPU(MemObject): tracer = Param.InstTracer(default_tracer, "Instruction tracer") _cached_ports = [] - if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']: + if buildEnv['TARGET_ISA'] == 'x86' or \ + (buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']): _cached_ports = ["itb.walker.port", "dtb.walker.port"] _uncached_ports = [] |