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| author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
| commit | 2012202b06a620998709f605f8f8692ad718294d (patch) | |
| tree | 43a4817c6889723d480e7c66c0b22cfe022cb0ea /src/cpu/SConscript | |
| parent | b569f8f0ed8dcf32347f0d4f68d2d7572a5d1353 (diff) | |
| download | gem5-2012202b06a620998709f605f8f8692ad718294d.tar.xz | |
inorder/alpha-isa: create eaComp object visible to StaticInst through ISA
Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access
* * *
Diffstat (limited to 'src/cpu/SConscript')
| -rw-r--r-- | src/cpu/SConscript | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/SConscript b/src/cpu/SConscript index 344deb9cf..854db9f12 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -49,6 +49,8 @@ execfile(models_db.srcnode().abspath) # Template for execute() signature. exec_sig_template = ''' virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0; +virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const +{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const { panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; virtual Fault completeAcc(Packet *pkt, %(type)s *xc, @@ -59,6 +61,8 @@ virtual int memAccSize(%(type)s *xc) ''' mem_ini_sig_template = ''' +virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const +{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; ''' |