arch: ISA parser additions of vector registers

Reiley's update :) of the isa parser definitions. My addition of the
vector element operand concept for the ISA parser. Nathanael's modification
creating a hierarchy between vector registers and its constituencies to the
isa parser.

Some fixes/updates on top to consider instructions as vectors instead of
floating when they use the VectorRF. Some counters added to all the
models to keep faithful counts.

Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2706
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py
index ef29726fc..55ef456ce 100644
--- a/src/cpu/StaticInstFlags.py
+++ b/src/cpu/StaticInstFlags.py
@@ -58,6 +58,8 @@ class StaticInstFlags(Enum):
         'IsInteger',        # References integer regs.
         'IsFloating',       # References FP regs.
         'IsCC',             # References CC regs.
+        'IsVector',         # References Vector regs.
+        'IsVectorElem',     # References Vector reg elems.
 
         'IsMemRef',         # References memory (load, store, or prefetch)
         'IsLoad',           # Reads from memory (load or prefetch).