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author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
commit | 8aaa39e93dfe000ad423b585e78a4c2ee7418363 (patch) | |
tree | 0f7b6d1efb630745bd6bf6af05a722a08c8640cb /src/cpu/base.hh | |
parent | 7e104a1af235823e3d641a972ea920937f7ec67d (diff) | |
download | gem5-8aaa39e93dfe000ad423b585e78a4c2ee7418363.tar.xz |
mem: Add a master ID to each request object.
This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
Diffstat (limited to 'src/cpu/base.hh')
-rw-r--r-- | src/cpu/base.hh | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 8250338cc..93e5476ef 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -104,6 +104,12 @@ class BaseCPU : public MemObject // therefore no setCpuId() method is provided int _cpuId; + /** instruction side request id that must be placed in all requests */ + MasterID _instMasterId; + + /** data side request id that must be placed in all requests */ + MasterID _dataMasterId; + /** * Define a base class for the CPU ports (instruction and data) * that is refined in the subclasses. This class handles the @@ -144,6 +150,11 @@ class BaseCPU : public MemObject /** Reads this CPU's ID. */ int cpuId() { return _cpuId; } + /** Reads this CPU's unique data requestor ID */ + MasterID dataMasterId() { return _dataMasterId; } + /** Reads this CPU's unique instruction requestor ID */ + MasterID instMasterId() { return _instMasterId; } + // Tick currentTick; inline Tick frequency() const { return SimClock::Frequency / clock; } inline Tick ticks(int numCycles) const { return clock * numCycles; } |