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author | Gabe Black <gblack@eecs.umich.edu> | 2007-04-08 01:42:42 +0000 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-04-08 01:42:42 +0000 |
commit | 3bb5fd8c44bbac6cbcfd18aed5fd46c112d19d7f (patch) | |
tree | d1fdb51884273fe9aa826312597f7f874d8f7c10 /src/cpu/base_dyn_inst.hh | |
parent | 3c9768e6448b72689e9edb250dd0ee3e5eadb9d7 (diff) | |
download | gem5-3bb5fd8c44bbac6cbcfd18aed5fd46c112d19d7f.tar.xz |
Get the "hard" SPARC instructions working in o3. I don't like that the IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly.
--HG--
extra : convert_revision : cfd32808592832d7b6fbdaace5ae7b17c8a246e9
Diffstat (limited to 'src/cpu/base_dyn_inst.hh')
-rw-r--r-- | src/cpu/base_dyn_inst.hh | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 6c6d90076..eed05c2f1 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -877,6 +877,11 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) effAddrValid = true; physEffAddr = req->getPaddr(); memReqFlags = req->getFlags(); + + if (req->isCondSwap()) { + assert(res); + req->setExtraData(*res); + } #if 0 if (cpu->system->memctrl->badaddr(physEffAddr)) { fault = TheISA::genMachineCheckFault(); |