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path: root/src/cpu/base_dyn_inst.hh
AgeCommit message (Expand)Author
2019-05-31fix nameis-iftIru Cai
2019-04-12add IFT optionsIru Cai
2019-04-08implement taint propagationIru Cai
2019-04-03check loads using tainted registers, set USL dst as taintedIru Cai
2019-04-02methods to set taintIru Cai
2019-03-20invisispec-1.0 sourceIru Cai
2018-11-16cpu: Fix the usage of const DynInstPtrRekai Gonzalez-Alberquilla
2018-06-14cpu: add a new instruction type 'Atomic'Tuan Ta
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
2018-06-11misc: Substitute pointer to Request with aliased RequestPtrGiacomo Travaglini
2018-01-09cpu: Add a NotAnInst flag to the BaseDynInst class.Gabe Black
2018-01-09cpu, power: Get rid of the remnants of the EA computation insts.Gabe Black
2017-07-05arch: ISA parser additions of vector registersRekai Gonzalez-Alberquilla
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-05cpu: Result refactoringRekai Gonzalez-Alberquilla
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
2017-07-05cpu: Physical register structural + flat indexingNathanael Premillieu
2017-07-05arch, cpu: Architectural Register structural indexingNathanael Premillieu
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
2016-04-05mem: Remove threadId from memory request classMitch Hayenga
2016-01-17cpu. arch: add initiateMemRead() to ExecContext interfaceSteve Reinhardt
2016-01-17cpu: remove unnecessary data ptr from O3 internal read() funcsSteve Reinhardt
2016-01-11scons: Enable -Wextra by defaultAndreas Hansson
2015-09-30cpu: Add per-thread monitorsMitch Hayenga
2015-09-15cpu, o3: consider split requests for LSQ checksnoop operationsHongil Yoon
2015-08-07base: Declare a type for context IDsAndreas Sandberg
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-05-15misc: Appease gcc 5.1Andreas Hansson
2015-05-05mem, cpu: Add a separate flag for strictly ordered memoryAndreas Sandberg
2015-03-02cpu: o3 register renaming request handling improvedRekai
2015-02-11sim: Move the BaseTLB to src/arch/generic/Andreas Sandberg
2015-01-25sim: Clean up InstRecordAli Saidi
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
2014-10-16arch: Use shared_ptr for all FaultsAndreas Hansson
2014-09-27arch: Use const StaticInstPtr references where possibleAndreas Hansson
2014-09-03arch, cpu: Factor out the ExecContext into a proper base classAndreas Sandberg
2014-05-09cpu, arm: Allow the specification of a socket fieldAkash Bagdia
2014-03-07cpu: Make CPU and ThreadContext getters constAndreas Hansson
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...Ali Saidi
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2013-10-17cpu: Fix O3 uncacheable load that is replayed but misses the TLBAli Saidi
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2012-06-05O3: Clean up the O3 structures and try to pack them a bit better.Ali Saidi
2012-06-05sim: Remove FastAllocAli Saidi
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
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