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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:15:44 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:15:44 -0800 |
| commit | 5605079b1f20bc7f6a4a80c8d1e4daabe7125270 (patch) | |
| tree | 29dfa1685e3e257e3857ef7f9672778d43582440 /src/cpu/base_dyn_inst.hh | |
| parent | a1aba01a02a8c1261120de83d8fbfd6624f0cb17 (diff) | |
| download | gem5-5605079b1f20bc7f6a4a80c8d1e4daabe7125270.tar.xz | |
ISA: Replace the translate functions in the TLBs with translateAtomic.
Diffstat (limited to 'src/cpu/base_dyn_inst.hh')
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index f58bf7cf8..41c57cf39 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -860,7 +860,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) req->setVirt(asid, addr, sizeof(T), flags, this->PC); req->setThreadContext(thread->contextId(), threadNumber); - fault = cpu->dtb->translate(req, thread->getTC(), false); + fault = cpu->dtb->translateAtomic(req, thread->getTC(), false); if (req->isUncacheable()) isUncacheable = true; @@ -916,7 +916,7 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) req->setVirt(asid, addr, sizeof(T), flags, this->PC); req->setThreadContext(thread->contextId(), threadNumber); - fault = cpu->dtb->translate(req, thread->getTC(), true); + fault = cpu->dtb->translateAtomic(req, thread->getTC(), true); if (req->isUncacheable()) isUncacheable = true; |