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| author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
| tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/cpu/base_dyn_inst.hh | |
| parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
| download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz | |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/cpu/base_dyn_inst.hh')
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 6d9a53253..84a6540af 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -82,9 +82,6 @@ class BaseDynInst : public ExecContext, public RefCounted typedef typename Impl::CPUType ImplCPU; typedef typename ImplCPU::ImplState ImplState; - // Logical register index type. - typedef TheISA::RegIndex RegIndex; - // The DynInstPtr type. typedef typename Impl::DynInstPtr DynInstPtr; typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; @@ -265,7 +262,7 @@ class BaseDynInst : public ExecContext, public RefCounted /** Flattened register index of the destination registers of this * instruction. */ - std::array<TheISA::RegIndex, TheISA::MaxInstDestRegs> _flatDestRegIdx; + std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx; /** Physical register index of the destination registers of this * instruction. @@ -386,7 +383,7 @@ class BaseDynInst : public ExecContext, public RefCounted /** Returns the flattened register index of the i'th destination * register. */ - TheISA::RegIndex flattenedDestRegIdx(int idx) const + RegId flattenedDestRegIdx(int idx) const { return _flatDestRegIdx[idx]; } @@ -422,7 +419,7 @@ class BaseDynInst : public ExecContext, public RefCounted /** Flattens a destination architectural register index into a logical * index. */ - void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) + void flattenDestReg(int idx, RegId flattened_dest) { _flatDestRegIdx[idx] = flattened_dest; } @@ -604,10 +601,10 @@ class BaseDynInst : public ExecContext, public RefCounted int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } /** Returns the logical register index of the i'th destination register. */ - RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } + RegId destRegIdx(int i) const { return staticInst->destRegIdx(i); } /** Returns the logical register index of the i'th source register. */ - RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } + RegId srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } /** Pops a result off the instResult queue */ template <class T> |