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| author | Tuan Ta <qtt2@cornell.edu> | 2018-02-12 23:19:50 -0500 |
|---|---|---|
| committer | Tuan Ta <qtt2@cornell.edu> | 2018-06-14 22:41:30 +0000 |
| commit | 7341f14f147337810325b19bac20db095b162911 (patch) | |
| tree | f8c5e2795048a110d216b4ad7108456bdaead5f8 /src/cpu/base_dyn_inst.hh | |
| parent | 78fb2c1a5d5e422bf14f134d677a83e3022238f1 (diff) | |
| download | gem5-7341f14f147337810325b19bac20db095b162911.tar.xz | |
cpu: add a new instruction type 'Atomic'
This patch adds a new flag named 'Atomic' to support ISA implementations
that use AtomicOpFunctor to handle atomic instructions instead of a
pair of locking load and unlocking store.
Change-Id: I1fbee6e54432396cb49dfc59ad9006b75812d115
Reviewed-on: https://gem5-review.googlesource.com/8187
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Diffstat (limited to 'src/cpu/base_dyn_inst.hh')
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 2c08a3c67..93cafd694 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -505,6 +505,7 @@ class BaseDynInst : public ExecContext, public RefCounted bool isMemRef() const { return staticInst->isMemRef(); } bool isLoad() const { return staticInst->isLoad(); } bool isStore() const { return staticInst->isStore(); } + bool isAtomic() const { return staticInst->isAtomic(); } bool isStoreConditional() const { return staticInst->isStoreConditional(); } bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } |