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| author | Marc Orr <morr@cs.wisc.edu> | 2014-11-06 05:42:22 -0600 |
|---|---|---|
| committer | Marc Orr <morr@cs.wisc.edu> | 2014-11-06 05:42:22 -0600 |
| commit | bf80734b2ce080cd75f4b57be47e37465e8901f1 (patch) | |
| tree | 0ba9cbba64cd017e95b5a3f637d58435208ebc3c /src/cpu/base_dyn_inst.hh | |
| parent | 3947f88d0fa35d2134fa3e999e05bb184a01e396 (diff) | |
| download | gem5-bf80734b2ce080cd75f4b57be47e37465e8901f1.tar.xz | |
x86 isa: This patch attempts an implementation at mwait.
Mwait works as follows:
1. A cpu monitors an address of interest (monitor instruction)
2. A cpu calls mwait - this loads the cache line into that cpu's cache.
3. The cpu goes to sleep.
4. When another processor requests write permission for the line, it is
evicted from the sleeping cpu's cache. This eviction is forwarded to the
sleeping cpu, which then wakes up.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/cpu/base_dyn_inst.hh')
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 289627c9a..af4d238e2 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -853,6 +853,14 @@ class BaseDynInst : public ExecContext, public RefCounted /** Sets the number of consecutive store conditional failures. */ void setStCondFailures(unsigned int sc_failures) { thread->storeCondFailures = sc_failures; } + + public: + // monitor/mwait funtions + void armMonitor(Addr address) { cpu->armMonitor(address); } + bool mwait(PacketPtr pkt) { return cpu->mwait(pkt); } + void mwaitAtomic(ThreadContext *tc) + { return cpu->mwaitAtomic(tc, cpu->dtb); } + AddressMonitor *getAddrMonitor() { return cpu->getCpuAddrMonitor(); } }; template<class Impl> |