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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-08 22:21:27 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-08 22:21:27 -0700 |
| commit | 7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60 (patch) | |
| tree | 4c212f665de2628eac6f84d389de7a79b6d0b933 /src/cpu/checker | |
| parent | 08043c777f1f05f5e14581950013461f328965be (diff) | |
| download | gem5-7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60.tar.xz | |
tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
Diffstat (limited to 'src/cpu/checker')
| -rw-r--r-- | src/cpu/checker/cpu.hh | 7 | ||||
| -rw-r--r-- | src/cpu/checker/thread_context.hh | 4 |
2 files changed, 5 insertions, 6 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 0d3dddded..3b378700e 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -49,8 +49,7 @@ #if FULL_SYSTEM namespace TheISA { - class ITB; - class DTB; + class TLB; } class Processor; class PhysicalMemory; @@ -130,8 +129,8 @@ class CheckerCPU : public BaseCPU ThreadContext *tc; - TheISA::ITB *itb; - TheISA::DTB *dtb; + TheISA::TLB *itb; + TheISA::TLB *dtb; #if FULL_SYSTEM Addr dbg_vtophys(Addr addr); diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index 3c87f841f..6b21bf670 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -84,9 +84,9 @@ class CheckerThreadContext : public ThreadContext int cpuId() { return actualTC->cpuId(); } - TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); } + TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } - TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); } + TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } #if FULL_SYSTEM System *getSystemPtr() { return actualTC->getSystemPtr(); } |