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author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-26 10:21:20 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-26 10:21:20 -0500 |
commit | 608641e23c7f2288810c3f23a1a63790b664f2ab (patch) | |
tree | 0656aaf9653e8d263f5daac0d5f0fe3190193ae5 /src/cpu/exec_context.hh | |
parent | 6e354e82d9395b20f5f148cd545d0666b626e8ac (diff) | |
download | gem5-608641e23c7f2288810c3f23a1a63790b664f2ab.tar.xz |
cpu: implements vector registers
This adds a vector register type. The type is defined as a std::array of a
fixed number of uint64_ts. The isa_parser.py has been modified to parse vector
register operands and generate the required code. Different cpus have vector
register files now.
Diffstat (limited to 'src/cpu/exec_context.hh')
-rw-r--r-- | src/cpu/exec_context.hh | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index c65841db2..5c6b3fad7 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -76,6 +76,7 @@ class ExecContext { typedef TheISA::MiscReg MiscReg; typedef TheISA::CCReg CCReg; + typedef TheISA::VectorReg VectorReg; public: /** @@ -128,6 +129,22 @@ class ExecContext { /** * @{ + * @name Vector Register Interfaces + * + */ + + /** Reads a vector register. */ + virtual const VectorReg &readVectorRegOperand (const StaticInst *si, + int idx) = 0; + + /** Sets a vector register to a value. */ + virtual void setVectorRegOperand(const StaticInst *si, + int idx, const VectorReg &val) = 0; + + /** @} */ + + /** + * @{ * @name Misc Register Interfaces */ virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0; |