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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-31 22:28:13 -0800 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-31 22:28:13 -0800 |
| commit | 4e00cc9900ec4f61899ee5be0c5b3827487e91f5 (patch) | |
| tree | 372809113645b16ab99adb5c4b81d7f3512780e5 /src/cpu/inorder/InOrderCPU.py | |
| parent | deb97742c7ada2008ec79aaf1791f7db3c6a2b06 (diff) | |
| parent | 04466ab4ca04a4e1e195a6f68423792b2553dadb (diff) | |
| download | gem5-4e00cc9900ec4f61899ee5be0c5b3827487e91f5.tar.xz | |
merge
Diffstat (limited to 'src/cpu/inorder/InOrderCPU.py')
| -rw-r--r-- | src/cpu/inorder/InOrderCPU.py | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index a0b0466a7..d6db346d4 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -30,10 +30,15 @@ from m5.params import * from m5.proxy import * from BaseCPU import BaseCPU +class ThreadModel(Enum): + vals = ['Single', 'SMT', 'SwitchOnCacheMiss'] + class InOrderCPU(BaseCPU): type = 'InOrderCPU' activity = Param.Unsigned(0, "Initial count") + threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)") + cachePorts = Param.Unsigned(2, "Cache Ports") stageWidth = Param.Unsigned(1, "Stage width") |