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| author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:40 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:40 -0400 |
| commit | 561c33f0824a705cb360ecb4ae3bf8cfd490f007 (patch) | |
| tree | 7fb92ebc9a8f09ceacb8ad8e60e60990a9939621 /src/cpu/inorder/cpu.hh | |
| parent | c4deabfb97928f81acb0d66338426cb5f2687c37 (diff) | |
| download | gem5-561c33f0824a705cb360ecb4ae3bf8cfd490f007.tar.xz | |
inorder: dont handle multiple faults on same cycle
if a faulting instruction reaches an execution unit,
then ignore it and pass it through the pipeline.
Once we recognize the fault in the graduation unit,
dont allow a second fault to creep in on the same cycle.
Diffstat (limited to 'src/cpu/inorder/cpu.hh')
| -rw-r--r-- | src/cpu/inorder/cpu.hh | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 8a0f2167b..a1e92f302 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -319,6 +319,7 @@ class InOrderCPU : public BaseCPU SkedCacheIt endOfSkedIt; ThePipeline::RSkedPtr frontEndSked; + ThePipeline::RSkedPtr faultSked; /** Add a new instruction schedule to the schedule cache */ void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked) @@ -366,6 +367,7 @@ class InOrderCPU : public BaseCPU } ThePipeline::RSkedPtr createFrontEndSked(); + ThePipeline::RSkedPtr createFaultSked(); ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst); class StageScheduler { @@ -751,7 +753,7 @@ class InOrderCPU : public BaseCPU virtual void wakeup(); #endif - // LL/SC debug functionality + /* LL/SC debug functionality unsigned stCondFails; unsigned readStCondFailures() @@ -759,6 +761,7 @@ class InOrderCPU : public BaseCPU unsigned setStCondFailures(unsigned st_fails) { return stCondFails = st_fails; } + */ /** Returns a pointer to a thread context. */ ThreadContext *tcBase(ThreadID tid = 0) |