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| author | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
|---|---|---|
| committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
| commit | 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch) | |
| tree | 040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/cpu/inorder/cpu.hh | |
| parent | 552622184752dc798bc81f9b0b395db68aee9511 (diff) | |
| download | gem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz | |
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Diffstat (limited to 'src/cpu/inorder/cpu.hh')
| -rw-r--r-- | src/cpu/inorder/cpu.hh | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index d5a31cca8..1183f6fc9 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -93,6 +93,7 @@ class InOrderCPU : public BaseCPU typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; + typedef TheISA::CCReg CCReg; typedef TheISA::MiscReg MiscReg; typedef TheISA::RegIndex RegIndex; @@ -327,6 +328,9 @@ class InOrderCPU : public BaseCPU FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs]; } floatRegs; TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs]; +#ifdef ISA_HAS_CC_REGS + TheISA::CCReg ccRegs[ThePipeline::MaxThreads][TheISA::NumCCRegs]; +#endif /** ISA state */ std::vector<TheISA::ISA *> isa; @@ -590,12 +594,16 @@ class InOrderCPU : public BaseCPU FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid); + CCReg readCCReg(RegIndex reg_idx, ThreadID tid); + void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid); void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid); void setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid); + void setCCReg(RegIndex reg_idx, CCReg val, ThreadID tid); + RegIndex flattenRegIdx(RegIndex reg_idx, RegClass ®_type, ThreadID tid); /** Reads a miscellaneous register. */ |