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| author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:35 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:35 -0400 |
| commit | 73cfab8b234c595e86413d4f7169bddc1a1184dd (patch) | |
| tree | 065463faacd0279cbffc033948224cd336c53b16 /src/cpu/inorder/resources | |
| parent | 4f34bc8b7ba3ef73fa0511560869c7a22c1b187c (diff) | |
| download | gem5-73cfab8b234c595e86413d4f7169bddc1a1184dd.tar.xz | |
inorder: DynInst handling of stores for big-endian ISAs
The DynInst was not performing the host-to-guest translation
which ended up breaking stores for SPARC
Diffstat (limited to 'src/cpu/inorder/resources')
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index c38e5541d..c1a3590be 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -840,6 +840,12 @@ CacheUnit::doCacheAccess(DynInstPtr inst, uint64_t *write_res, } else { cache_req->dataPkt->dataStatic(&cache_req->inst->storeData); } + + DPRINTF(InOrderCachePort, + "[tid:%u]: [sn:%i]: Storing data: %s\n", + tid, inst->seqNum, + printMemData(cache_req->dataPkt->getPtr<uint8_t>(), + cache_req->dataPkt->getSize())); if (cache_req->memReq->isCondSwap()) { assert(write_res); |