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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-03 20:23:00 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-03 20:23:00 -0800 |
| commit | 00f24ae92c7b9aa73e12fd8160b5756e80126db2 (patch) | |
| tree | 1d149846db0efdc77c635891c6c1433d3af1817d /src/cpu/inorder | |
| parent | 869a046e413d7cbfdda4e33eed8191004017a83f (diff) | |
| download | gem5-00f24ae92c7b9aa73e12fd8160b5756e80126db2.tar.xz | |
Config: Keep track of uncached and cached ports separately.
This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
Diffstat (limited to 'src/cpu/inorder')
| -rw-r--r-- | src/cpu/inorder/InOrderCPU.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index d6db346d4..8e25891e7 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -46,7 +46,7 @@ class InOrderCPU(BaseCPU): dataMemPort = Param.String("dcache_port" , "Name of Memory Port to get data from") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") - _mem_ports = ['icache_port', 'dcache_port'] + _cached_ports = ['icache_port', 'dcache_port'] predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") localPredictorSize = Param.Unsigned(2048, "Size of local predictor") |