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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-05-13 12:20:48 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-05-13 12:20:48 -0500 |
| commit | e3b19cb294c98466a431950888045c6b5d24b675 (patch) | |
| tree | 781bcf5ea9fdce45a5747a4d5ef74485ee5e0727 /src/cpu/inorder | |
| parent | afbae1ec95e94b6da441a0269dbd9359a7069e3d (diff) | |
| download | gem5-e3b19cb294c98466a431950888045c6b5d24b675.tar.xz | |
mem: Refactor assignment of Packet types
Put the packet type swizzling (that is currently done in a lot of places)
into a refineCommand() member function.
Diffstat (limited to 'src/cpu/inorder')
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index c71678a91..dea4f91fb 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -812,21 +812,11 @@ CacheUnit::finishCacheUnitReq(DynInstPtr inst, CacheRequest *cache_req) void CacheUnit::buildDataPacket(CacheRequest *cache_req) { - // Check for LL/SC and if so change command - if (cache_req->memReq->isLLSC() && cache_req->pktCmd == MemCmd::ReadReq) { - cache_req->pktCmd = MemCmd::LoadLockedReq; - } - - if (cache_req->pktCmd == MemCmd::WriteReq) { - cache_req->pktCmd = - cache_req->memReq->isSwap() ? MemCmd::SwapReq : - (cache_req->memReq->isLLSC() ? MemCmd::StoreCondReq - : MemCmd::WriteReq); - } - cache_req->dataPkt = new CacheReqPacket(cache_req, cache_req->pktCmd, cache_req->instIdx); + cache_req->dataPkt->refineCommand(); // handle LL/SC, etc. + DPRINTF(InOrderCachePort, "[slot:%i]: Slot marked for %x\n", cache_req->getSlot(), cache_req->dataPkt->getAddr()); |