diff options
author | Lisa Hsu <hsul@eecs.umich.edu> | 2006-12-13 14:33:32 -0500 |
---|---|---|
committer | Lisa Hsu <hsul@eecs.umich.edu> | 2006-12-13 14:33:32 -0500 |
commit | a983c4968cebeb9c2b67957934ffd26eb914b525 (patch) | |
tree | 082f2ce4a061d3c05b29d6a2cb5e5478c80120d4 /src/cpu/o3/alpha/dyn_inst.hh | |
parent | 4947bf276eaa19d33c1af0bd0843dc23192fdd19 (diff) | |
parent | 5d42fd836b88c1a234a5d7ddd768422f9878e2df (diff) | |
download | gem5-a983c4968cebeb9c2b67957934ffd26eb914b525.tar.xz |
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision : c6d174716641f0b8286b8478bcb9053b3eec54e3
Diffstat (limited to 'src/cpu/o3/alpha/dyn_inst.hh')
-rw-r--r-- | src/cpu/o3/alpha/dyn_inst.hh | 35 |
1 files changed, 19 insertions, 16 deletions
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh index 31df8ff78..49cc5a201 100644 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ b/src/cpu/o3/alpha/dyn_inst.hh @@ -163,27 +163,28 @@ class AlphaDynInst : public BaseDynInst<Impl> // storage (which is pretty hard to imagine they would have reason // to do). - uint64_t readIntReg(const StaticInst *si, int idx) + uint64_t readIntRegOperand(const StaticInst *si, int idx) { return this->cpu->readIntReg(_srcRegIdx[idx]); } - FloatReg readFloatReg(const StaticInst *si, int idx, int width) + FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) { return this->cpu->readFloatReg(_srcRegIdx[idx], width); } - FloatReg readFloatReg(const StaticInst *si, int idx) + FloatReg readFloatRegOperand(const StaticInst *si, int idx) { return this->cpu->readFloatReg(_srcRegIdx[idx]); } - FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, + int width) { return this->cpu->readFloatRegBits(_srcRegIdx[idx], width); } - FloatRegBits readFloatRegBits(const StaticInst *si, int idx) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { return this->cpu->readFloatRegBits(_srcRegIdx[idx]); } @@ -191,35 +192,37 @@ class AlphaDynInst : public BaseDynInst<Impl> /** @todo: Make results into arrays so they can handle multiple dest * registers. */ - void setIntReg(const StaticInst *si, int idx, uint64_t val) + void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) { this->cpu->setIntReg(_destRegIdx[idx], val); - BaseDynInst<Impl>::setIntReg(si, idx, val); + BaseDynInst<Impl>::setIntRegOperand(si, idx, val); } - void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, + int width) { this->cpu->setFloatReg(_destRegIdx[idx], val, width); - BaseDynInst<Impl>::setFloatReg(si, idx, val, width); + BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width); } - void setFloatReg(const StaticInst *si, int idx, FloatReg val) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { this->cpu->setFloatReg(_destRegIdx[idx], val); - BaseDynInst<Impl>::setFloatReg(si, idx, val); + BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); } - void setFloatRegBits(const StaticInst *si, int idx, - FloatRegBits val, int width) + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val, int width) { this->cpu->setFloatRegBits(_destRegIdx[idx], val, width); - BaseDynInst<Impl>::setFloatRegBits(si, idx, val); + BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); } - void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val) { this->cpu->setFloatRegBits(_destRegIdx[idx], val); - BaseDynInst<Impl>::setFloatRegBits(si, idx, val); + BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); } /** Returns the physical register index of the i'th destination |