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| author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-31 15:50:11 +0800 |
| commit | a4c6e88d766858b675a7fd256df5a8b9a7e18ada (patch) | |
| tree | a00f59eea3e87c31eb9efbce9f8d6f397ae16db2 /src/cpu/o3/cpu.cc | |
| parent | 866b200c202dded37fdd857a1a42ec149bd109c9 (diff) | |
| download | gem5-a4c6e88d766858b675a7fd256df5a8b9a7e18ada.tar.xz | |
import invisispec-1.0 source by Mengjia Yan
The original code is at https://github.com/mjyan0720/InvisiSpec-1.0
This code is rebased on upstream gem5 commit 866b200c, which features:
- rdtscp support
- some C++ code optimizations
- newer Linux kernel version number in SE mode
Diffstat (limited to 'src/cpu/o3/cpu.cc')
| -rw-r--r-- | src/cpu/o3/cpu.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 2f793453d..b298b9baa 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -593,6 +593,7 @@ FullO3CPU<Impl>::tick() activityRec.advance(); + DPRINTF(O3CPU, "activityRec.advance() complete\n"); if (removeInstsThisCycle) { cleanUpRemovedInsts(); } @@ -610,6 +611,8 @@ FullO3CPU<Impl>::tick() schedule(tickEvent, clockEdge(Cycles(1))); DPRINTF(O3CPU, "Scheduling next tick!\n"); } + } else { + DPRINTF(O3CPU, "tickEvent.scheduled == false, %lu", curTick()); } if (!FullSystem) |