| Age | Commit message (Expand) | Author |
|---|
| 2019-05-31 | implement taint propagation | Iru Cai |
| 2019-05-31 | check loads using tainted registers, set USL dst as tainted | Iru Cai |
| 2019-05-31 | methods to set taint | Iru Cai |
| 2019-05-31 | import invisispec-1.0 source by Mengjia Yan | Iru Cai |
| 2018-11-16 | cpu: Fix the usage of const DynInstPtr | Rekai Gonzalez-Alberquilla |
| 2017-11-21 | cpu, cpu, sim: move Cycle probe update | Jose Marinho |
| 2017-11-20 | pwr: Adds logic to enter power gating for the cpu model | Anouk Van Laer |
| 2017-07-17 | cpu,o3: Fixed checkpointing bug occuring in the o3 CPU | Anouk Van Laer |
| 2017-07-12 | cpu: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Simplify the rename interface and use RegId | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Physical register structural + flat indexing | Nathanael Premillieu |
| 2017-07-05 | arch, cpu: Architectural Register structural indexing | Nathanael Premillieu |
| 2015-07-20 | syscall_emul: [patch 13/22] add system call retry capability | Brandon Potter |
| 2016-11-09 | style: [patch 1/22] use /r/3648/ to reorganize includes | Brandon Potter |
| 2016-09-13 | sim: Refactor quiesce and remove FS asserts | Michael LeBeane |
| 2016-06-06 | pwr: Low-power idle power state for idle CPUs | David Guillen Fandos |
| 2016-04-06 | Revert power patch sets with unexpected interactions | Andreas Sandberg |
| 2014-12-09 | power: Low-power idle power state for idle CPUs | Akash Bagdia |
| 2015-12-31 | mem: Make cache terminology easier to understand | Andreas Hansson |
| 2015-12-07 | probe: Add probe in Fetch, IEW, Rename and Commit | Radhika Jagtap |
| 2015-11-22 | cpu: Fix base FP and CC register index in o3 insertThread() | Nathanael Premillieu |
| 2015-09-30 | cpu,isa,mem: Add per-thread wakeup logic | Mitch Hayenga |
| 2015-09-30 | isa,cpu: Add support for FS SMT Interrupts | Mitch Hayenga |
| 2015-09-30 | cpu: Add per-thread monitors | Mitch Hayenga |
| 2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
| 2015-07-26 | cpu: implements vector registers | Nilay Vaish |
| 2015-07-07 | sim: Refactor and simplify the drain API | Andreas Sandberg |
| 2015-07-07 | sim: Make the drain state a global typed enum | Andreas Sandberg |
| 2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
| 2015-05-05 | mem: Snoop into caches on uncacheable accesses | Andreas Hansson |
| 2015-04-03 | cpu: fix system total instructions accounting | Nikos Nikoleris |
| 2015-03-02 | mem: Split port retry for all different packet classes | Andreas Hansson |
| 2015-02-16 | arch: Make readMiscRegNoEffect const throughout | Andreas Hansson |
| 2015-02-06 | cpu: Idle CPU status logic revised | Alexandru Dutu |
| 2014-11-06 | x86 isa: This patch attempts an implementation at mwait. | Marc Orr |
| 2014-10-20 | cpu: o3: corrects base FP and CC register index in removeThread() | Nilay Vaish |
| 2014-10-16 | cpu: Probe points for basic PMU stats | Andreas Sandberg |
| 2014-09-27 | arch: Use const StaticInstPtr references where possible | Andreas Hansson |
| 2014-09-20 | cpu: Remove unused deallocateContext calls | Mitch Hayenga |
| 2014-09-20 | alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate | Mitch Hayenga |
| 2014-09-19 | arch: Pass faults by const reference where possible | Andreas Hansson |
| 2014-09-03 | cpu: Fix SMT scheduling issue with the O3 cpu | Mitch Hayenga |
| 2014-06-21 | o3: split load & store queue full cases in rename | Binh Pham |
| 2014-05-23 | cpu: o3: remove stat totalCommittedInsts | Nilay Vaish |
| 2014-04-19 | o3: Fix occupancy checks for SMT | Faissal Sleiman |
| 2014-01-24 | base: add support for probe points and common probes | Matt Horsnell |
| 2013-12-03 | cpu: call BaseCPU startup() function in o3 cpu | Nilay Vaish |
| 2013-10-31 | cpu: Construct ROB with cpu params struct instead of each variable | Faissal Sleiman |
| 2013-10-15 | cpu: add a condition-code register class | Yasuko Eckert |
