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path: root/src/cpu/o3/cpu.cc
AgeCommit message (Expand)Author
2019-05-31implement taint propagationIru Cai
2019-05-31check loads using tainted registers, set USL dst as taintedIru Cai
2019-05-31methods to set taintIru Cai
2019-05-31import invisispec-1.0 source by Mengjia YanIru Cai
2018-11-16cpu: Fix the usage of const DynInstPtrRekai Gonzalez-Alberquilla
2017-11-21cpu, cpu, sim: move Cycle probe updateJose Marinho
2017-11-20pwr: Adds logic to enter power gating for the cpu modelAnouk Van Laer
2017-07-17cpu,o3: Fixed checkpointing bug occuring in the o3 CPUAnouk Van Laer
2017-07-12cpu: Refactor some Event subclasses to lambdasSean Wilson
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
2017-07-05cpu: Physical register structural + flat indexingNathanael Premillieu
2017-07-05arch, cpu: Architectural Register structural indexingNathanael Premillieu
2015-07-20syscall_emul: [patch 13/22] add system call retry capabilityBrandon Potter
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2016-09-13sim: Refactor quiesce and remove FS assertsMichael LeBeane
2016-06-06pwr: Low-power idle power state for idle CPUsDavid Guillen Fandos
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
2014-12-09power: Low-power idle power state for idle CPUsAkash Bagdia
2015-12-31mem: Make cache terminology easier to understandAndreas Hansson
2015-12-07probe: Add probe in Fetch, IEW, Rename and CommitRadhika Jagtap
2015-11-22cpu: Fix base FP and CC register index in o3 insertThread()Nathanael Premillieu
2015-09-30cpu,isa,mem: Add per-thread wakeup logicMitch Hayenga
2015-09-30isa,cpu: Add support for FS SMT InterruptsMitch Hayenga
2015-09-30cpu: Add per-thread monitorsMitch Hayenga
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-07-07sim: Make the drain state a global typed enumAndreas Sandberg
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-05-05mem: Snoop into caches on uncacheable accessesAndreas Hansson
2015-04-03cpu: fix system total instructions accountingNikos Nikoleris
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-02-16arch: Make readMiscRegNoEffect const throughoutAndreas Hansson
2015-02-06cpu: Idle CPU status logic revisedAlexandru Dutu
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
2014-10-20cpu: o3: corrects base FP and CC register index in removeThread()Nilay Vaish
2014-10-16cpu: Probe points for basic PMU statsAndreas Sandberg
2014-09-27arch: Use const StaticInstPtr references where possibleAndreas Hansson
2014-09-20cpu: Remove unused deallocateContext callsMitch Hayenga
2014-09-20alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivateMitch Hayenga
2014-09-19arch: Pass faults by const reference where possibleAndreas Hansson
2014-09-03cpu: Fix SMT scheduling issue with the O3 cpuMitch Hayenga
2014-06-21o3: split load & store queue full cases in renameBinh Pham
2014-05-23cpu: o3: remove stat totalCommittedInstsNilay Vaish
2014-04-19o3: Fix occupancy checks for SMTFaissal Sleiman
2014-01-24base: add support for probe points and common probesMatt Horsnell
2013-12-03cpu: call BaseCPU startup() function in o3 cpuNilay Vaish
2013-10-31cpu: Construct ROB with cpu params struct instead of each variableFaissal Sleiman
2013-10-15cpu: add a condition-code register classYasuko Eckert