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invisispec-with-dift
is-ift
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is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
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cpu
Age
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Author
2019-05-31
fix the violation checking for IFT+fence
Iru Cai
2019-05-31
add a trackBranch option
Iru Cai
2019-05-31
IFT for fence scheme
Iru Cai
2019-05-31
track instruction after tainted branches
Iru Cai
2019-05-31
Add IFT debug flags
Iru Cai
2019-05-31
add IEW DPRINTF
Iru Cai
2019-05-31
keep time to expose as original scheme when inst->needPostFetch()
Iru Cai
2019-05-31
add IFT options
Iru Cai
2019-05-31
clear taint when previous branch resolved
Iru Cai
2019-05-31
we need to ++loadsToVLD when (!inst->readyToExpose() && inst->needPostFetch())
Iru Cai
2019-05-31
implement taint propagation
Iru Cai
2019-05-31
check loads using tainted registers, set USL dst as tainted
Iru Cai
2019-05-31
methods to set taint
Iru Cai
2019-05-31
add taint map
Iru Cai
2019-05-31
print load inst
Iru Cai
2019-05-31
import invisispec-1.0 source by Mengjia Yan
Iru Cai
2018-12-11
cpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctor
Tony Gutierrez
2018-12-04
base, sim: Add missing destructors
Nikos Nikoleris
2018-12-03
cpu: Change raw pointers to STL Containers
Rekai Gonzalez-Alberquilla
2018-11-28
cpu: Added new stats to TAGE and LTAGE branch predictors
Pau Cabre
2018-11-28
cpu: split LTAGE implementation into a base TAGE and a derived LTAGE
Pau Cabre
2018-11-28
cpu,arch-arm: Initialise data members
Rekai Gonzalez-Alberquilla
2018-11-27
arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.
Gabe Black
2018-11-22
cpu: Made LTAGE parameters configurable
Pau Cabre
2018-11-22
cpu: Fixed useful counter handling in LTAGE
Pau Cabre
2018-11-22
cpu: Fixes on the loop predictor part of LTAGE
Pau Cabre
2018-11-17
cpu: Fix LTAGE max number of allocations on update
Pau Cabre
2018-11-17
configs: Added an option for choosing branch predictor type
Pau Cabre
2018-11-16
cpu: Fix the usage of const DynInstPtr
Rekai Gonzalez-Alberquilla
2018-11-14
cpu: Fixed ratio of pred to hyst bits for LTAGE Bimodal
Pau Cabre
2018-11-13
cpu: Fixed PC shifting on LTAGE branch predictor
Pau Cabre
2018-10-09
cpu: Fix MinorCPU executing Crypto Instructions
Giacomo Travaglini
2018-10-09
arch-arm: AArch32 Crypto AES
Matt Horsnell
2018-10-09
arch-arm: AArch32 Crypto SHA
Matt Horsnell
2018-10-01
cpu: Fix typo in header guard for Noncaching cpu
Giacomo Travaglini
2018-09-13
Fix SConstruct for asan build
Earl Ou
2018-09-12
cpu: Replace the fastmem with a new CPU model
Andreas Sandberg
2018-08-24
cpu: Stream/SubstreamID support in TrafficGen
Giacomo Travaglini
2018-08-24
cpu: Turn BaseTrafficGen numSuppressed into a stat
Michiel W. van Tol
2018-08-21
misc: Appease GCC 8
Jason Lowe-Power
2018-08-17
scons,ruby: do not generate unnecessary files
Brandon Potter
2018-08-10
cpu: Add hash functionality for RegId class
Bradley Wang
2018-08-10
cpu: Removed unnecessary file reg_class_impl.hh
Bradley Wang
2018-07-25
cpu: Warn when (un)serializing a traffic generator
Giacomo Travaglini
2018-07-25
cpu: Allow creation of traffic gen from generic SimObjects
Giacomo Travaglini
2018-07-24
cpu-o3: Missing freeing the heads of DepGraph in IQ squashing
Hanhwi Jang
2018-07-13
cpu: Add a Python-enabled traffic generator
Andreas Sandberg
2018-07-13
cpu: Support trace termination in BaseTrafficGen
Andreas Sandberg
2018-07-13
cpu: Unify error handling for address generators
Andreas Sandberg
2018-07-13
cpu: Split the traffic generator into two classes
Andreas Sandberg
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