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author | Gabe Black <gblack@eecs.umich.edu> | 2007-04-14 17:13:18 +0000 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-04-14 17:13:18 +0000 |
commit | c3081d9c1c36e1a08c173048783d191fa19463de (patch) | |
tree | f2717bd70d64af1e6ef54ff73e3cbee7984f4b31 /src/cpu/o3/cpu.cc | |
parent | 5a3dcc172a9fd661330909815b163eb6f4d6a2d8 (diff) | |
download | gem5-c3081d9c1c36e1a08c173048783d191fa19463de.tar.xz |
Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
--HG--
extra : convert_revision : 8b9c603616bcad254417a7a3fa3edfb4c8728719
Diffstat (limited to 'src/cpu/o3/cpu.cc')
-rw-r--r-- | src/cpu/o3/cpu.cc | 30 |
1 files changed, 29 insertions, 1 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index b2b4645d2..59978a065 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -696,7 +696,7 @@ FullO3CPU<Impl>::removeThread(unsigned tid) // Squash Throughout Pipeline InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; - fetch.squash(0, sizeof(TheISA::MachInst), squash_seq_num, tid); + fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); decode.squash(tid); rename.squash(squash_seq_num, tid); iew.squash(tid); @@ -1152,6 +1152,20 @@ FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) template <class Impl> uint64_t +FullO3CPU<Impl>::readMicroPC(unsigned tid) +{ + return commit.readMicroPC(tid); +} + +template <class Impl> +void +FullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid) +{ + commit.setMicroPC(new_PC, tid); +} + +template <class Impl> +uint64_t FullO3CPU<Impl>::readNextPC(unsigned tid) { return commit.readNextPC(tid); @@ -1179,6 +1193,20 @@ FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) } template <class Impl> +uint64_t +FullO3CPU<Impl>::readNextMicroPC(unsigned tid) +{ + return commit.readNextMicroPC(tid); +} + +template <class Impl> +void +FullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid) +{ + commit.setNextMicroPC(new_PC, tid); +} + +template <class Impl> typename FullO3CPU<Impl>::ListIt FullO3CPU<Impl>::addInst(DynInstPtr &inst) { |