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authorGabe Black <gabeblack@google.com>2020-01-09 02:10:15 -0800
committerGabe Black <gabeblack@google.com>2020-01-23 00:51:57 +0000
commit0b8d02dec492215aa286138404d9fc1f0b7a9074 (patch)
tree272153d238c25958e48e09a3511f249dcc1e8605 /src/cpu/o3/cpu.cc
parentae7dd927e2978cee89d6828b31ab991aa6de40e2 (diff)
downloadgem5-0b8d02dec492215aa286138404d9fc1f0b7a9074.tar.xz
cpu: Consolidate and move the CPU's calls to TheISA::initCPU.
TheISA::initCPU is basically an ISA specific implementation of reset logic on architectural state. As such, it only needs to be called if we're not going to load a checkpoint, ie in initState. Also, since the implementation was the same across all CPUs, this change collapses all the individual implementations down into the base CPU class. Change-Id: Id68133fd7f31619c90bf7b3aad35ae20871acaa4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24189 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/o3/cpu.cc')
-rw-r--r--src/cpu/o3/cpu.cc7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 996f6360b..e4f1c0464 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -599,13 +599,6 @@ FullO3CPU<Impl>::init()
thread[tid]->initMemProxies(thread[tid]->getTC());
}
- if (FullSystem && !params()->switched_out) {
- for (ThreadID tid = 0; tid < numThreads; tid++) {
- ThreadContext *src_tc = threadContexts[tid];
- TheISA::initCPU(src_tc, src_tc->contextId());
- }
- }
-
// Clear noSquashFromTC.
for (int tid = 0; tid < numThreads; ++tid)
thread[tid]->noSquashFromTC = false;