| Age | Commit message (Expand) | Author |
|---|
| 2020-01-23 | cpu: Consolidate and move the CPU's calls to TheISA::initCPU. | Gabe Black |
| 2019-12-10 | arch,cpu,sim: Push syscall number determination up to processes. | Gabe Black |
| 2019-10-25 | cpu: Get rid of the serviceInstCountEvents method. | Gabe Black |
| 2019-10-25 | cpu: Access inst events through ThreadContext instead of the CPU. | Gabe Black |
| 2019-10-25 | cpu: Make accesses to comInstEventQueue indirect through methods. | Gabe Black |
| 2019-10-15 | sim,cpu: Get rid of the unused instEventQueue. | Gabe Black |
| 2019-08-28 | cpu: Move the instruction port into o3's fetch stage. | Gabe Black |
| 2019-08-28 | cpu: Move O3's data port into the LSQ. | Gabe Black |
| 2019-07-16 | cpu: isDrained renamed to isCpuDrained | Giacomo Travaglini |
| 2019-05-18 | arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code. | Gabe Black |
| 2019-04-30 | cpu: alpha: Delete all occurrances of the simPalCheck function. | Gabe Black |
| 2019-04-30 | cpu: Remove hwrei from the generic interfaces. | Gabe Black |
| 2019-04-30 | arch: cpu: Track kernel stats using the base ISA agnostic type. | Gabe Black |
| 2019-04-03 | misc: Removed inconsistency in O3* debug msgs | Andrea Mondelli |
| 2019-03-28 | cpu: Added a probe to notify the address of retired instructions | Javier Bueno |
| 2019-02-08 | sim,cpu: make exit_group halt all threads in a group | Tuan Ta |
| 2019-02-08 | cpu: fixed how O3 CPU executes an exit system call | Tuan Ta |
| 2019-02-01 | cpu, arch: Replace the CCReg type with RegVal. | Gabe Black |
| 2019-01-31 | arch: cpu: Rename *FloatRegBits* to *FloatReg*. | Gabe Black |
| 2019-01-30 | arch,cpu: Add vector predicate registers | Giacomo Gabrielli |
| 2019-01-25 | cpu, arch, arch-arm: Wire unused VecElem code in the O3 model | Giacomo Travaglini |
| 2019-01-25 | cpu: Fix VecElemClass bugs in cpu models | Giacomo Travaglini |
| 2019-01-24 | cpu-o3: O3 LSQ Generalisation | Rekai Gonzalez-Alberquilla |
| 2019-01-22 | arch: cpu: Stop passing around misc registers by reference. | Gabe Black |
| 2019-01-16 | cpu: dev: sim: gpu-compute: Banish some ISA specific register types. | Gabe Black |
| 2019-01-15 | cpu: Fix usage of setArchVecElem | Giacomo Travaglini |
| 2018-12-20 | arch, cpu: Remove float type accessors. | Gabe Black |
| 2018-11-16 | cpu: Fix the usage of const DynInstPtr | Rekai Gonzalez-Alberquilla |
| 2017-11-21 | cpu, cpu, sim: move Cycle probe update | Jose Marinho |
| 2017-11-20 | pwr: Adds logic to enter power gating for the cpu model | Anouk Van Laer |
| 2017-07-17 | cpu,o3: Fixed checkpointing bug occuring in the o3 CPU | Anouk Van Laer |
| 2017-07-12 | cpu: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Simplify the rename interface and use RegId | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Physical register structural + flat indexing | Nathanael Premillieu |
| 2017-07-05 | arch, cpu: Architectural Register structural indexing | Nathanael Premillieu |
| 2015-07-20 | syscall_emul: [patch 13/22] add system call retry capability | Brandon Potter |
| 2016-11-09 | style: [patch 1/22] use /r/3648/ to reorganize includes | Brandon Potter |
| 2016-09-13 | sim: Refactor quiesce and remove FS asserts | Michael LeBeane |
| 2016-06-06 | pwr: Low-power idle power state for idle CPUs | David Guillen Fandos |
| 2016-04-06 | Revert power patch sets with unexpected interactions | Andreas Sandberg |
| 2014-12-09 | power: Low-power idle power state for idle CPUs | Akash Bagdia |
| 2015-12-31 | mem: Make cache terminology easier to understand | Andreas Hansson |
| 2015-12-07 | probe: Add probe in Fetch, IEW, Rename and Commit | Radhika Jagtap |
| 2015-11-22 | cpu: Fix base FP and CC register index in o3 insertThread() | Nathanael Premillieu |
| 2015-09-30 | cpu,isa,mem: Add per-thread wakeup logic | Mitch Hayenga |
| 2015-09-30 | isa,cpu: Add support for FS SMT Interrupts | Mitch Hayenga |
| 2015-09-30 | cpu: Add per-thread monitors | Mitch Hayenga |
| 2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
| 2015-07-26 | cpu: implements vector registers | Nilay Vaish |
