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authorGiacomo Gabrielli <Giacomo.Gabrielli@arm.com>2011-02-11 18:29:35 -0600
committerGiacomo Gabrielli <Giacomo.Gabrielli@arm.com>2011-02-11 18:29:35 -0600
commite2507407b17188dca802082434cfe0230d9bfa61 (patch)
tree6913f9325a7c2fc9c6e99119c61f014e10707842 /src/cpu/o3/fetch.hh
parent453dbc772dba92dbceb44eaeef3c617d17d63e84 (diff)
downloadgem5-e2507407b17188dca802082434cfe0230d9bfa61.tar.xz
O3: Enhance data address translation by supporting hardware page table walkers.
Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs, when a TLB miss occurs, initiateTranslation() can return with NoFault but with the translation unfinished. Instructions experiencing a delayed translation due to a hardware page table walk are deferred until the translation completes and kept into the IQ. In order to keep track of them, the IQ has been augmented with a queue of the outstanding delayed memory instructions. When their translation completes, instructions are re-executed (only their initiateAccess() was already executed; their DTB translation is now skipped). The IEW stage has been modified to support such a 2-pass execution.
Diffstat (limited to 'src/cpu/o3/fetch.hh')
-rw-r--r--src/cpu/o3/fetch.hh4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 92691720b..647c48a76 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -137,6 +137,10 @@ class DefaultFetch
{}
void
+ markDelayed()
+ {}
+
+ void
finish(Fault fault, RequestPtr req, ThreadContext *tc,
BaseTLB::Mode mode)
{