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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-02-07 11:35:48 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-12-05 11:47:01 +0000 |
| commit | 099cb037e83d1e7bb47ec0e8eaf649a63f889d38 (patch) | |
| tree | da6877f00070e243cb83c233fb5debfdf82a15e2 /src/cpu/o3/lsq_unit.hh | |
| parent | 3deff78fe40b9aa3d4e3a8571f13f29072efe4e4 (diff) | |
| download | gem5-099cb037e83d1e7bb47ec0e8eaf649a63f889d38.tar.xz | |
cpu: Add support for CMOs in the cpu models
Cache maintenance operations go through the write channel of the
cpu. This changes makes sure that the cpu does not try to fill in the
packet with data.
Change-Id: Ic83205bb1cda7967636d88f15adcb475eb38d158
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5055
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/o3/lsq_unit.hh')
| -rw-r--r-- | src/cpu/o3/lsq_unit.hh | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index b8e895571..a2813b3dc 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2014 ARM Limited + * Copyright (c) 2012-2014,2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -650,10 +650,14 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, store_size = storeQueue[store_idx].size; - if (store_size == 0) - continue; - else if (storeQueue[store_idx].inst->strictlyOrdered()) + if (!store_size || storeQueue[store_idx].inst->strictlyOrdered() || + (storeQueue[store_idx].req && + storeQueue[store_idx].req->isCacheMaintenance())) { + // Cache maintenance instructions go down via the store + // path but they carry no data and they shouldn't be + // considered for forwarding continue; + } assert(storeQueue[store_idx].inst->effAddrValid()); @@ -894,9 +898,9 @@ LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh, storeQueue[store_idx].sreqHigh = sreqHigh; unsigned size = req->getSize(); storeQueue[store_idx].size = size; - storeQueue[store_idx].isAllZeros = req->getFlags() & Request::CACHE_BLOCK_ZERO; - assert(size <= sizeof(storeQueue[store_idx].data) || - (req->getFlags() & Request::CACHE_BLOCK_ZERO)); + bool store_no_data = req->getFlags() & Request::STORE_NO_DATA; + storeQueue[store_idx].isAllZeros = store_no_data; + assert(size <= sizeof(storeQueue[store_idx].data) || store_no_data); // Split stores can only occur in ISAs with unaligned memory accesses. If // a store request has been split, sreqLow and sreqHigh will be non-null. @@ -904,7 +908,8 @@ LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh, storeQueue[store_idx].isSplit = true; } - if (!(req->getFlags() & Request::CACHE_BLOCK_ZERO)) + if (!(req->getFlags() & Request::CACHE_BLOCK_ZERO) && \ + !req->isCacheMaintenance()) memcpy(storeQueue[store_idx].data, data, size); // This function only writes the data to the store queue, so no fault |