gem5 - gem5

Age	Commit message (Expand)	Author
2019-05-12	only spec load when hit	Iru Cai
2019-05-11	try not expose if L1 hitis-ift-cachehit	Iru Cai
2019-04-17	add a trackBranch option	Iru Cai
2019-04-12	add IFT options	Iru Cai
2019-04-01	fix getvaddr nullptr stuff, add a non-spec load printingis-rebase11-LSQUnit	Iru Cai
2019-03-21	Request::getVaddr()	Iru Cai
2019-03-20	invisispec-1.0 source	Iru Cai
2018-12-03	cpu: Change raw pointers to STL Containers	Rekai Gonzalez-Alberquilla
2018-11-16	cpu: Fix the usage of const DynInstPtr	Rekai Gonzalez-Alberquilla
2018-06-11	misc: Using smart pointers for memory Requests	Giacomo Travaglini
2018-06-11	misc: Substitute pointer to Request with aliased RequestPtr	Giacomo Travaglini
2017-12-05	cpu: Add support for CMOs in the cpu models	Nikos Nikoleris
2017-08-30	cpu-o3: fix data pkt initialization for split load	Matthias Hille
2017-05-15	cpu: fix problem with forwarding and locked load	Alec Roelke
2016-12-21	cpu: Clarify meaning of cachePorts variable in lsq_unit.hh of O3	Arthur Perais
2016-01-17	cpu: remove unnecessary data ptr from O3 internal read() funcs	Steve Reinhardt
2015-10-12	misc: Remove redundant compiler-specific defines	Andreas Hansson
2015-05-05	mem, cpu: Add a separate flag for strictly ordered memory	Andreas Sandberg
2014-11-14	arm: Fixes based on UBSan and static analysis	Andreas Hansson
2014-10-16	arch: Use shared_ptr for all Faults	Andreas Hansson
2014-05-13	mem: Refactor assignment of Packet types	Curtis Dunham
2014-09-03	cpu: Fix cache blocked load behavior in o3 cpu	Mitch Hayenga
2014-09-03	cpu: Change writeback modeling for outstanding instructions	Mitch Hayenga
2014-06-21	o3: split load & store queue full cases in rename	Binh Pham
2014-04-01	cpu: Fix case where o3 lsq could print out uninitialized data	Mitch Hayenga
2014-01-24	cpu: Add support for instructions that zero cache lines.	Ali Saidi
2013-01-07	cpu: Rewrite O3 draining to avoid stopping in microcode	Andreas Sandberg
2013-01-07	cpu: Fix O3 LSQ debug dumping constness and formatting	Andreas Sandberg
2012-12-06	o3 cpu: remove some unused buggy functions in the lsq	Nathanael Premillieu
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-28	Clock: Rework clocks to avoid tick-to-cycle transformations	Andreas Hansson
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-02-07	Faults: Turn off arch/faults.hh	Gabe Black
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	clang: Enable compiling gem5 using clang 2.9 and 3.0	Koan-Sin Tan
2012-01-29	Yet another merge with the main repository.	Gabe Black
2012-01-28	O3 CPU LSQ: Implement TSO	Nilay Vaish
2011-11-18	SE/FS: Get rid of includes of config/full_system.hh.	Gabe Black
2011-09-27	Faults: Replace calls to genMachineCheckFault with M5PanicFault.	Gabe Black
2011-09-13	LSQ: Only trigger a memory violation with a load/load if the value changes.	Ali Saidi
2011-08-16	O3: Make lsq_unit.hh include arch/isa_traits.hh directly, not transitively.	Gabe Black
2011-07-31	O3: Implement memory mapped IPRs for O3.	Gabe Black
2011-05-23	O3: Fix offset calculation into storeQueue buffer for store->load forwarding	Geoffrey Blake
2011-05-23	O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.	Geoffrey Blake
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert