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author | Iru Cai <mytbk920423@gmail.com> | 2019-05-11 21:41:14 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-11 21:41:14 +0800 |
commit | 2b62fec3590024a7ce82ef5d4647397d37ed37eb (patch) | |
tree | 8f4a6d9bed9d5006f3d5d9ac94b1b6b5fa8d5578 /src/cpu/o3/lsq_unit.hh | |
parent | 3b26d5f86c9a427e6ab9b9fa688b76ab2034a0d2 (diff) | |
download | gem5-2b62fec3590024a7ce82ef5d4647397d37ed37eb.tar.xz |
try not expose if L1 hitis-ift-cachehit
Diffstat (limited to 'src/cpu/o3/lsq_unit.hh')
-rw-r--r-- | src/cpu/o3/lsq_unit.hh | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index fbe5248f7..1c8b98f2e 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -1045,7 +1045,6 @@ LSQUnit<Impl>::read(const RequestPtr &req, " req=%#x\n", load_inst->seqNum, load_inst->postReq->getVaddr()); } - load_inst->needDeletePostReq(true); } else { load_inst->setExposeCompleted(); load_inst->needPostFetch(false); |