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| author | Iru Cai <mytbk920423@gmail.com> | 2019-04-17 10:54:51 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-04-17 10:54:51 +0800 |
| commit | 30488f4a29e9092e0d0dd304ec113dcc92e171f4 (patch) | |
| tree | fff1e24c94b44f8fbaa2fff3f9b676ca337b6d21 /src/cpu/o3/lsq_unit.hh | |
| parent | bf35a9ab1e9664846c9e03c9ffa5eba589bed159 (diff) | |
| download | gem5-30488f4a29e9092e0d0dd304ec113dcc92e171f4.tar.xz | |
add a trackBranch option
Diffstat (limited to 'src/cpu/o3/lsq_unit.hh')
| -rw-r--r-- | src/cpu/o3/lsq_unit.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index c512ef819..fbe5248f7 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -529,6 +529,7 @@ class LSQUnit { bool isFuturistic; bool allowSpecBuffHit; bool useIFT; + bool trackBranch; /* [mengjia] different schemes determine values of 4 variables. */ // Will also need how many read/write ports the Dcache has. Or keep track |