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authorGabe Black <gblack@eecs.umich.edu>2011-09-27 00:24:43 -0700
committerGabe Black <gblack@eecs.umich.edu>2011-09-27 00:24:43 -0700
commit44ed4849d468b8188bdfc273c8e9a03a8f31c263 (patch)
treedb5907e0a478d4a9e6e479a53a478412d5284a47 /src/cpu/o3/lsq_unit.hh
parent2ed3eef9b046472ef20a6c7829e3aa1814d929fb (diff)
downloadgem5-44ed4849d468b8188bdfc273c8e9a03a8f31c263.tar.xz
Faults: Replace calls to genMachineCheckFault with M5PanicFault.
Diffstat (limited to 'src/cpu/o3/lsq_unit.hh')
-rw-r--r--src/cpu/o3/lsq_unit.hh5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index af926759c..3c1af4533 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -38,6 +38,7 @@
#include <queue>
#include "arch/faults.hh"
+#include "arch/generic/debugfaults.hh"
#include "arch/isa_traits.hh"
#include "arch/locked_mem.hh"
#include "arch/mmapped_ipr.hh"
@@ -568,7 +569,9 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
delete sreqLow;
delete sreqHigh;
}
- return TheISA::genMachineCheckFault();
+ return new GenericISA::M5PanicFault(
+ "Uncachable load [sn:%llx] PC %s\n",
+ load_inst->seqNum, load_inst->pcState());
}
// Check the SQ for any previous stores that might lead to forwarding