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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-31 11:51:19 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-31 11:51:19 -0500 |
| commit | 4590b91fb8842f6a3b823bbc06334132de43d54b (patch) | |
| tree | 72a17ff25a0be08e4bc3576ff9e179974817c722 /src/cpu/o3/lsq_unit.hh | |
| parent | 4fdecae443c4f11d24b7da537b6f7a2baadbd130 (diff) | |
| download | gem5-4590b91fb8842f6a3b823bbc06334132de43d54b.tar.xz | |
MEM: Remove the otherPort from the cache ports
This patch is a very straight-forward simplification, removing the
unecessary otherPort pointer from the cache port. The pointer was only
used to forward range changes, and the address range is fixed for the
cache. Removing the pointer simplifies the transition to master/slave
ports.
Diffstat (limited to 'src/cpu/o3/lsq_unit.hh')
0 files changed, 0 insertions, 0 deletions