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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2017-03-29 14:07:03 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-05-15 14:50:14 +0000 |
| commit | 8ced1bd0b0f9890992bcf9f517df5e33839621c7 (patch) | |
| tree | 1a93637f9f1216bc44988968255fedaa1bd5f2b3 /src/cpu/o3/lsq_unit.hh | |
| parent | c6a6fbe9fdf3b7d586f83d50522ce2b91b3f2ba9 (diff) | |
| download | gem5-8ced1bd0b0f9890992bcf9f517df5e33839621c7.tar.xz | |
arm, dev: stub out GIC distributor interrupt groups
We don't implement the GICD_IGROUPRn registers, which is allowed, but
to be correct, they should be RAZ/WI (read as zero, writes ignored).
Change-Id: I8039baf72f45c0095f41e165b8e327c79b1ac082
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2620
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/o3/lsq_unit.hh')
0 files changed, 0 insertions, 0 deletions