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author | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-03 07:42:33 -0400 |
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committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-03 07:42:33 -0400 |
commit | 976f27487b57e968a326752fcf74747427733df6 (patch) | |
tree | 16c9e61f702f21d82948b1f5b555ef1b7c543b15 /src/cpu/o3/lsq_unit.hh | |
parent | fd722946dd723bda5bd4aea5eedbda108141a550 (diff) | |
download | gem5-976f27487b57e968a326752fcf74747427733df6.tar.xz |
cpu: Change writeback modeling for outstanding instructions
As highlighed on the mailing list gem5's writeback modeling can impact
performance. This patch removes the limitation on maximum outstanding issued
instructions, however the number that can writeback in a single cycle is still
respected in instToCommit().
Diffstat (limited to 'src/cpu/o3/lsq_unit.hh')
-rw-r--r-- | src/cpu/o3/lsq_unit.hh | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 00469197d..fcefa42fd 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -762,7 +762,6 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, // Tell IQ/mem dep unit that this instruction will need to be // rescheduled eventually iewStage->rescheduleMemInst(load_inst); - iewStage->decrWb(load_inst->seqNum); load_inst->clearIssued(); ++lsqRescheduledLoads; @@ -889,12 +888,6 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, ++lsqCacheBlocked; - // If the first part of a split access succeeds, then let the LSQ - // handle the decrWb when completeDataAccess is called upon return - // of the requested first part of data - if (!completedFirst) - iewStage->decrWb(load_inst->seqNum); - // There's an older load that's already going to squash. if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum) return NoFault; |