summaryrefslogtreecommitdiff
path: root/src/cpu/o3/lsq_unit.hh
diff options
context:
space:
mode:
authorDeyuan Guo <guodeyuan@tsinghua.org.cn>2011-09-10 03:45:25 -0700
committerDeyuan Guo <guodeyuan@tsinghua.org.cn>2011-09-10 03:45:25 -0700
commitbb921b1459ef3ec55f9cea4ac8d203cd3c801cfd (patch)
tree8978bf2fc84bb36393c243d67751738ada856d70 /src/cpu/o3/lsq_unit.hh
parent6a2b223112d60e4efe14fcf9863a14cde93df82e (diff)
downloadgem5-bb921b1459ef3ec55f9cea4ac8d203cd3c801cfd.tar.xz
MIPS: Implement gem5/src/arch/mips/remote_gdb.cc.
So a mips-cross-gdb can connect with gem5(MIPS_SE), and do some remote debugging. Testing: Build gem5 for MIPS_SE and make gem5 wait at beginning: modify "rgdb_wait = -1" to "rgdb_wait = 0" in src/sim/system.cc; scons build/MIPS_SE/gem5.opt CPU_MODELS=O3CPU ---- Build GDB-7.3 mips-cross: ./configure --target=mips-linux-gnu --prefix=xxx/gdb-7.3-install/ make make install ---- Run: ./build/MIPS_SE/gem5.opt configs/example/se.py --detailed --caches ./mips-linux-gnu-gdb xxx/gem5/tests/test-progs/hello/bin/mips/linux/hello (gdb) target remote :7000 (gdb) info registers (gdb) disassemble (gdb) si (gdb) break main (gdb) c (gdb) quit Testing done.
Diffstat (limited to 'src/cpu/o3/lsq_unit.hh')
0 files changed, 0 insertions, 0 deletions