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| author | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-23 11:18:40 -0500 |
|---|---|---|
| committer | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-23 11:18:40 -0500 |
| commit | 43c938d23e2b28c7190bd10c470c452676f5cb9d (patch) | |
| tree | d6176dc000ff7dd2d0789ae92f6318791e3e6f27 /src/cpu/o3/lsq_unit.hh | |
| parent | 5f91ec3f4618dad8d36efbf8b5a5112a1ce0d1b7 (diff) | |
| download | gem5-43c938d23e2b28c7190bd10c470c452676f5cb9d.tar.xz | |
O3: Handle loads when the destination is the PC.
For loads that PC is the destination, check if the load
was mispredicted again when the value being loaded returns from memory
Diffstat (limited to 'src/cpu/o3/lsq_unit.hh')
| -rw-r--r-- | src/cpu/o3/lsq_unit.hh | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 10b1ed11a..a9047558d 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -530,6 +530,8 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, (load_idx != loadHead || !load_inst->isAtCommit())) { iewStage->rescheduleMemInst(load_inst); ++lsqRescheduledLoads; + DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %#x\n", + load_inst->seqNum, load_inst->readPC()); // Must delete request now that it wasn't handed off to // memory. This is quite ugly. @todo: Figure out the proper |