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authorGabe Black <gblack@eecs.umich.edu>2011-07-31 19:21:17 -0700
committerGabe Black <gblack@eecs.umich.edu>2011-07-31 19:21:17 -0700
commit206c2e9a0ee04e00100dde25da9b15cbfbaac0d6 (patch)
tree518901a34efc50696a201d5640caca1948c2a5ae /src/cpu/o3/lsq_unit.hh
parent6308ca27ff357fb9bbb1250d93a7058ef69c7602 (diff)
downloadgem5-206c2e9a0ee04e00100dde25da9b15cbfbaac0d6.tar.xz
O3: Implement memory mapped IPRs for O3.
Diffstat (limited to 'src/cpu/o3/lsq_unit.hh')
-rw-r--r--src/cpu/o3/lsq_unit.hh38
1 files changed, 38 insertions, 0 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index d83dc868f..2076d67d1 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -39,6 +39,7 @@
#include "arch/faults.hh"
#include "arch/locked_mem.hh"
+#include "arch/mmapped_ipr.hh"
#include "base/fast_alloc.hh"
#include "base/hashmap.hh"
#include "config/full_system.hh"
@@ -578,6 +579,43 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
load_inst->recordResult = true;
}
+ if (req->isMmappedIpr()) {
+ assert(!load_inst->memData);
+ load_inst->memData = new uint8_t[64];
+
+ ThreadContext *thread = cpu->tcBase(lsqID);
+ Tick delay;
+ PacketPtr data_pkt =
+ new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+
+ if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
+ data_pkt->dataStatic(load_inst->memData);
+ delay = TheISA::handleIprRead(thread, data_pkt);
+ } else {
+ assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr());
+ PacketPtr fst_data_pkt =
+ new Packet(sreqLow, MemCmd::ReadReq, Packet::Broadcast);
+ PacketPtr snd_data_pkt =
+ new Packet(sreqHigh, MemCmd::ReadReq, Packet::Broadcast);
+
+ fst_data_pkt->dataStatic(load_inst->memData);
+ snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
+
+ delay = TheISA::handleIprRead(thread, fst_data_pkt);
+ unsigned delay2 = TheISA::handleIprRead(thread, snd_data_pkt);
+ if (delay2 > delay)
+ delay = delay2;
+
+ delete sreqLow;
+ delete sreqHigh;
+ delete fst_data_pkt;
+ delete snd_data_pkt;
+ }
+ WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
+ cpu->schedule(wb, curTick() + delay);
+ return NoFault;
+ }
+
while (store_idx != -1) {
// End once we've reached the top of the LSQ
if (store_idx == storeWBIdx) {