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| author | Matt Horsnell <matt.horsnell@ARM.com> | 2014-01-24 15:29:30 -0600 |
|---|---|---|
| committer | Matt Horsnell <matt.horsnell@ARM.com> | 2014-01-24 15:29:30 -0600 |
| commit | ca89eba79ebe0adc9cea7656c288e0381754171a (patch) | |
| tree | 10446c49e315ae891e625ccae48c050b4e48737a /src/cpu/o3/lsq_unit_impl.hh | |
| parent | daa781d2db938dcc7bea4455b03838fa5bf6ddbf (diff) | |
| download | gem5-ca89eba79ebe0adc9cea7656c288e0381754171a.tar.xz | |
mem: track per-request latencies and access depths in the cache hierarchy
Add some values and methods to the request object to track the translation
and access latency for a request and which level of the cache hierarchy responded
to the request.
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 77b67ac69..ade076995 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -129,6 +129,8 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) delete state->mainPkt->req; delete state->mainPkt; } + + pkt->req->setAccessLatency(); delete state; delete pkt->req; delete pkt; |