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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:49 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:49 -0600 |
| commit | ae3d45685512b75f878eb9d7917680fc3971988e (patch) | |
| tree | da8a195456de67473cb0a950600b3bcf4fb3d0ee /src/cpu/o3 | |
| parent | f05f35df99e2b9be3353d7585142b91139965e22 (diff) | |
| download | gem5-ae3d45685512b75f878eb9d7917680fc3971988e.tar.xz | |
ARM: Fix bug that let two table walks occur in parallel.
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/commit_impl.hh | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 50c08e162..01e235722 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -1142,6 +1142,8 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) commitStatus[tid] = TrapPending; + DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n", + head_inst->seqNum); if (head_inst->traceData) { if (DTRACE(ExecFaulting)) { head_inst->traceData->setFetchSeq(head_inst->seqNum); |