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authorIru Cai <mytbk920423@gmail.com>2019-04-12 01:22:41 +0800
committerIru Cai <mytbk920423@gmail.com>2019-04-12 01:31:32 +0800
commit101d6e356c630e9e0d48c0b3188807b8e5818c37 (patch)
tree9e96ba0f8bb8a5f25f469790080b5fd0211466e1 /src/cpu/o3
parent8fe7e974ee5ca80885b9231ec397e5681d67d3ae (diff)
downloadgem5-101d6e356c630e9e0d48c0b3188807b8e5818c37.tar.xz
keep time to expose as original scheme when inst->needPostFetch()
because when inst->needPostFetch(), it means that the spec load is already issued this also fixes the mysterious bug caused by the IFT code
Diffstat (limited to 'src/cpu/o3')
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh7
1 files changed, 2 insertions, 5 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 7ac85654e..a8ec0333f 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1056,18 +1056,15 @@ LSQUnit<Impl>::updateVisibleState()
} else {
/* set taint for dst registers */
inst->taintDestRegs(true);
- inst->isTainted = true;
/* if the load depends on tainted registers, set
readyToExpose to false, otherwise set it to true
*/
- if (inst->srcTainted()) {
+ bool doSpecLoad = inst->needPostFetch() || inst->srcTainted();
+ if (doSpecLoad) {
DPRINTF(LSQUnit, "load inst [sn:%lli] %s not safe, set readyToExpose to false\n", inst->seqNum, inst->pcState());
inst->readyToExpose(false);
} else {
DPRINTF(LSQUnit, "load inst [sn:%lli] %s is an unsafe speculated load, but source registers are not tainted.\n", inst->seqNum, inst->pcState());
- if (!inst->readyToExpose() && inst->needPostFetch()) {
- ++loadsToVLD;
- }
inst->readyToExpose(true);
}
}