Merge zizzer.eecs.umich.edu:/bk/newmem

into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 2711fec2bf72801999b060e65f0bf744c18734fb

10 files changed, 25 insertions, 14 deletions

diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index 9dee610b6..294aadde8 100644
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -86,7 +86,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
     Fault initiateAcc();
 
     /** Completes the access.  Only valid for memory operations. */
-    Fault completeAcc(Packet *pkt);
+    Fault completeAcc(PacketPtr pkt);
 
   private:
     /** Initializes variables. */
diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh
index 2d1b4b309..b273a7b9b 100644
--- a/src/cpu/o3/alpha/dyn_inst_impl.hh
+++ b/src/cpu/o3/alpha/dyn_inst_impl.hh
@@ -100,7 +100,7 @@ AlphaDynInst<Impl>::initiateAcc()
 
 template <class Impl>
 Fault
-AlphaDynInst<Impl>::completeAcc(Packet *pkt)
+AlphaDynInst<Impl>::completeAcc(PacketPtr pkt)
 {
     this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
 
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 4c9a8e91f..367508288 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -850,9 +850,6 @@ template <class Impl>
 void
 FullO3CPU<Impl>::resume()
 {
-#if FULL_SYSTEM
-    assert(system->getMemoryMode() == System::Timing);
-#endif
     fetch.resume();
     decode.resume();
     rename.resume();
@@ -864,6 +861,10 @@ FullO3CPU<Impl>::resume()
     if (_status == SwitchedOut || _status == Idle)
         return;
 
+#if FULL_SYSTEM
+    assert(system->getMemoryMode() == System::Timing);
+#endif
+
     if (!tickEvent.scheduled())
         tickEvent.schedule(curTick);
     _status = Running;
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 280bf0e71..5555bff85 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -36,7 +36,7 @@
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 #include "cpu/pc_event.hh"
-#include "mem/packet_impl.hh"
+#include "mem/packet.hh"
 #include "mem/port.hh"
 #include "sim/eventq.hh"
 
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 147c670de..e7bf83b20 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -78,9 +78,12 @@ DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
 
 template<class Impl>
 bool
-DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt)
+DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
 {
-    fetch->processCacheCompletion(pkt);
+    if (pkt->isResponse()) {
+        fetch->processCacheCompletion(pkt);
+    }
+    //else Snooped a coherence request, just return
     return true;
 }
 
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 7b7d1eb8e..317e23b14 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -63,7 +63,14 @@ template <class Impl>
 bool
 LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
 {
-    lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
+    if (pkt->isResponse()) {
+        lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
+    }
+    else {
+    //else it is a coherence request, maybe you need to do something
+        warn("Recieved a coherence request (Invalidate?), 03CPU doesn't"
+             "update LSQ for these\n");
+    }
     return true;
 }
 
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 11a02e7c7..1b207fdbc 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -40,7 +40,7 @@
 #include "config/full_system.hh"
 #include "base/hashmap.hh"
 #include "cpu/inst_seq.hh"
-#include "mem/packet_impl.hh"
+#include "mem/packet.hh"
 #include "mem/port.hh"
 
 /**
@@ -219,7 +219,7 @@ class LSQUnit {
     void writeback(DynInstPtr &inst, PacketPtr pkt);
 
     /** Handles completing the send of a store to memory. */
-    void storePostSend(Packet *pkt);
+    void storePostSend(PacketPtr pkt);
 
     /** Completes the store at the specified index. */
     void completeStore(int store_idx);
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 3f9db912f..d940d7cb3 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -763,7 +763,7 @@ LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
 
 template <class Impl>
 void
-LSQUnit<Impl>::storePostSend(Packet *pkt)
+LSQUnit<Impl>::storePostSend(PacketPtr pkt)
 {
     if (isStalled() &&
         storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh
index 06bdfcec4..aa30bfa1e 100755
--- a/src/cpu/o3/mips/dyn_inst.hh
+++ b/src/cpu/o3/mips/dyn_inst.hh
@@ -87,7 +87,7 @@ class MipsDynInst : public BaseDynInst<Impl>
     Fault initiateAcc();
 
     /** Completes the access.  Only valid for memory operations. */
-    Fault completeAcc(Packet *pkt);
+    Fault completeAcc(PacketPtr pkt);
 
   private:
     /** Initializes variables. */
diff --git a/src/cpu/o3/mips/dyn_inst_impl.hh b/src/cpu/o3/mips/dyn_inst_impl.hh
index 57dec1ccf..5bc01b9b3 100755
--- a/src/cpu/o3/mips/dyn_inst_impl.hh
+++ b/src/cpu/o3/mips/dyn_inst_impl.hh
@@ -100,7 +100,7 @@ MipsDynInst<Impl>::initiateAcc()
 
 template <class Impl>
 Fault
-MipsDynInst<Impl>::completeAcc(Packet *pkt)
+MipsDynInst<Impl>::completeAcc(PacketPtr pkt)
 {
     this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);