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authorGabe Black <gblack@eecs.umich.edu>2006-12-06 06:05:28 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-12-06 06:05:28 -0500
commit2dcf00bc8b6ca0bdfc8ab9a105f7a7780c763bb4 (patch)
treec34b7e7417d0c95255def0cea2a48a72229da344 /src/cpu/o3
parentbe29adf51cb115e7e55321bd58b7f6593e6d0080 (diff)
parent54a946604b2fa81c0d58fc41bfe1d82840f44793 (diff)
downloadgem5-2dcf00bc8b6ca0bdfc8ab9a105f7a7780c763bb4.tar.xz
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem src/cpu/o3/commit_impl.hh: Hand Merge --HG-- extra : convert_revision : 6984db90d5b5ec71c31f1c345f5a77eed540059e
Diffstat (limited to 'src/cpu/o3')
-rw-r--r--src/cpu/o3/commit_impl.hh1
-rw-r--r--src/cpu/o3/cpu.cc8
-rw-r--r--src/cpu/o3/fetch_impl.hh2
-rwxr-xr-xsrc/cpu/o3/thread_context.hh2
-rwxr-xr-xsrc/cpu/o3/thread_context_impl.hh6
5 files changed, 13 insertions, 6 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index ba6a62b4d..1527efe1a 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -733,7 +733,6 @@ DefaultCommit<Impl>::commit()
if (!squash_bdelay_slot)
bdelay_done_seq_num++;
-
#endif
if (fromIEW->includeSquashInst[tid] == true) {
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 3dc353a9f..a5a00015f 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -497,8 +497,6 @@ FullO3CPU<Impl>::init()
}
#if FULL_SYSTEM
- src_tc->init();
-
TheISA::initCPU(src_tc, src_tc->readCpuId());
#endif
}
@@ -554,6 +552,12 @@ template <class Impl>
void
FullO3CPU<Impl>::activateContext(int tid, int delay)
{
+#if FULL_SYSTEM
+ // Connect the ThreadContext's memory ports (Functional/Virtual
+ // Ports)
+ threadContexts[tid]->connectMemPorts();
+#endif
+
// Needs to set each stage to running as well.
if (delay){
DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 8213e8fa2..f9e90614a 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1139,6 +1139,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
ext_inst = TheISA::makeExtMI(inst, fetch_PC);
#elif THE_ISA == SPARC_ISA
ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
+#elif THE_ISA == MIPS_ISA
+ ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
#endif
// Create a new DynInst from the instruction fetched.
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 031f36480..390569c3d 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -92,7 +92,7 @@ class O3ThreadContext : public ThreadContext
void delVirtPort(VirtualPort *vp);
- virtual void init() { thread->init(); }
+ virtual void connectMemPorts() { thread->connectMemPorts(); }
#else
virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 29c00a0c3..af98fa1f5 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -102,8 +102,10 @@ template <class Impl>
void
O3ThreadContext<Impl>::delVirtPort(VirtualPort *vp)
{
- delete vp->getPeer();
- delete vp;
+ if (vp != thread->getVirtPort()) {
+ delete vp->getPeer();
+ delete vp;
+ }
}
#endif