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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-03-01 11:37:02 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-03-01 11:37:02 -0600 |
| commit | c80af04d7df7586352841a65a4398baf21e0c122 (patch) | |
| tree | 60292236eecafe541bc47bb9b987e6fb7d067dae /src/cpu/o3 | |
| parent | e11847bfa949481322f2031049402a093ed442a7 (diff) | |
| download | gem5-c80af04d7df7586352841a65a4398baf21e0c122.tar.xz | |
x86: Fix switching of CPUs
This patch prevents creation of interrupt controller for
cpus that will be switched in later
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/cpu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 7f24ee988..5dd2c3f3c 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -653,7 +653,7 @@ FullO3CPU<Impl>::init() if (icachePort.isConnected()) fetch.setIcache(); - if (FullSystem) { + if (FullSystem && !params()->defer_registration) { for (ThreadID tid = 0; tid < numThreads; tid++) { ThreadContext *src_tc = threadContexts[tid]; TheISA::initCPU(src_tc, src_tc->contextId()); |