diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2012-01-16 04:27:10 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2012-01-16 04:27:10 -0800 |
commit | da2a4acc26ba264c3c4a12495776fd6a1c4fb133 (patch) | |
tree | f142100388b9d1403492c97b0d323728ce18ef8a /src/cpu/o3 | |
parent | 241cc0c8402f1b9f2ec20d1cc152d96930959b2a (diff) | |
parent | a7394ad6807bd5e85f680184bf308673ca00534a (diff) | |
download | gem5-da2a4acc26ba264c3c4a12495776fd6a1c4fb133.tar.xz |
Merge yet again with the main repository.
Diffstat (limited to 'src/cpu/o3')
-rw-r--r-- | src/cpu/o3/commit_impl.hh | 3 | ||||
-rw-r--r-- | src/cpu/o3/decode_impl.hh | 4 | ||||
-rw-r--r-- | src/cpu/o3/iew_impl.hh | 6 | ||||
-rw-r--r-- | src/cpu/o3/rename_impl.hh | 4 |
4 files changed, 6 insertions, 11 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index c481d7b9c..b6a4c0387 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -51,6 +51,7 @@ #include "config/use_checker.hh" #include "cpu/o3/commit.hh" #include "cpu/o3/thread_state.hh" +#include "cpu/base.hh" #include "cpu/exetrace.hh" #include "cpu/timebuf.hh" #include "debug/Activity.hh" @@ -987,6 +988,8 @@ DefaultCommit<Impl>::commitInsts() // Updates misc. registers. head_inst->updateMiscRegs(); + cpu->traceFunctions(pc[tid].instAddr()); + TheISA::advancePC(pc[tid], head_inst->staticInst); // Keep track of the last sequence number commited diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh index 3def971e9..985e92826 100644 --- a/src/cpu/o3/decode_impl.hh +++ b/src/cpu/o3/decode_impl.hh @@ -446,10 +446,6 @@ void DefaultDecode<Impl>::sortInsts() { int insts_from_fetch = fromFetch->size; -#ifdef DEBUG - for (ThreadID tid = 0; tid < numThreads; tid++) - assert(insts[tid].empty()); -#endif for (int i = 0; i < insts_from_fetch; ++i) { insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); } diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index 9c4b1068d..92c8875e4 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -1340,10 +1340,10 @@ DefaultIEW<Impl>::executeInsts() fetchRedirect[tid] = true; DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); - DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", - inst->predInstAddr(), inst->predNextInstAddr()); + DPRINTF(IEW, "Predicted target was PC: %s.\n", + inst->readPredTarg()); DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", - inst->pcState(), inst->nextInstAddr()); + inst->pcState()); // If incorrect, then signal the ROB that it must be squashed. squashDueToBranch(inst, tid); diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 4106bbef9..04935604e 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -766,10 +766,6 @@ void DefaultRename<Impl>::sortInsts() { int insts_from_decode = fromDecode->size; -#ifdef DEBUG - for (ThreadID tid = 0; tid < numThreads; tid++) - assert(insts[tid].empty()); -#endif for (int i = 0; i < insts_from_decode; ++i) { DynInstPtr inst = fromDecode->insts[i]; insts[inst->threadNumber].push_back(inst); |