summaryrefslogtreecommitdiff
path: root/src/cpu/o3
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2012-01-07 02:15:35 -0800
committerGabe Black <gblack@eecs.umich.edu>2012-01-07 02:15:35 -0800
commitec936364b7238cddea7734ea79c6e04b52a683c6 (patch)
tree788fc19c3ba599d6f39d3990769888a0650be5ff /src/cpu/o3
parent36a822f08e88483b41af214ace4fd3dccf3aa8cb (diff)
parent9b52717a92ed9592bd98a41683509f538262a5c7 (diff)
downloadgem5-ec936364b7238cddea7734ea79c6e04b52a683c6.tar.xz
Merge with the main repository again.
Diffstat (limited to 'src/cpu/o3')
-rw-r--r--src/cpu/o3/O3CPU.py4
-rw-r--r--src/cpu/o3/cpu.cc13
-rw-r--r--src/cpu/o3/cpu.hh3
3 files changed, 16 insertions, 4 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 51643c169..1d8950a73 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -142,7 +142,3 @@ class DerivO3CPU(BaseCPU):
smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
- def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
- BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc)
- self.icache.tgts_per_mshr = 20
- self.dcache.tgts_per_mshr = 20
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index bb5ccc17e..5d3af6c70 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -438,6 +438,12 @@ FullO3CPU<Impl>::regStats()
"to idling")
.prereq(idleCycles);
+ quiesceCycles
+ .name(name() + ".quiesceCycles")
+ .desc("Total number of cycles that CPU has spent quiesced or waiting "
+ "for an interrupt")
+ .prereq(quiesceCycles);
+
// Number of Instructions simulated
// --------------------------------
// Should probably be in Base CPU but need templated
@@ -682,6 +688,8 @@ FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
activityRec.activity();
fetch.wakeFromQuiesce();
+ quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
+
lastActivatedCycle = curTick();
_status = Running;
@@ -716,6 +724,9 @@ FullO3CPU<Impl>::suspendContext(ThreadID tid)
if ((activeThreads.size() == 1 && !deallocated) ||
activeThreads.size() == 0)
unscheduleTickEvent();
+
+ DPRINTF(Quiesce, "Suspending Context\n");
+ lastRunningCycle = curTick();
_status = Idle;
}
@@ -1193,6 +1204,8 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
}
if (!tickEvent.scheduled())
schedule(tickEvent, nextCycle());
+
+ lastRunningCycle = curTick();
}
template <class Impl>
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index b5654dee1..7580106ad 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -713,6 +713,9 @@ class FullO3CPU : public BaseO3CPU
Stats::Scalar timesIdled;
/** Stat for total number of cycles the CPU spends descheduled. */
Stats::Scalar idleCycles;
+ /** Stat for total number of cycles the CPU spends descheduled due to a
+ * quiesce operation or waiting for an interrupt. */
+ Stats::Scalar quiesceCycles;
/** Stat for the number of committed instructions per thread. */
Stats::Vector committedInsts;
/** Stat for the total number of committed instructions. */