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| author | Vincentius Robby <acolyte@umich.edu> | 2007-08-08 18:43:12 -0400 |
|---|---|---|
| committer | Vincentius Robby <acolyte@umich.edu> | 2007-08-08 18:43:12 -0400 |
| commit | ec4000e0e284834df0eb1db792074a1b11f21cc8 (patch) | |
| tree | 9b42b9697c8fe3cf00c3ab8257002146d8d37a9c /src/cpu/simple/AtomicSimpleCPU.py | |
| parent | 1caed1465470269c36897904edddf8d4dc9765b1 (diff) | |
| download | gem5-ec4000e0e284834df0eb1db792074a1b11f21cc8.tar.xz | |
Added fastmem option.
Lets CPU accesses to physical memory bypass Bus.
--HG--
extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
Diffstat (limited to 'src/cpu/simple/AtomicSimpleCPU.py')
| -rw-r--r-- | src/cpu/simple/AtomicSimpleCPU.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index e97f059c1..bfd1825c2 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -40,4 +40,5 @@ class AtomicSimpleCPU(BaseCPU): profile = Param.Latency('0ns', "trace the kernel stack") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") - _mem_ports = ['icache_port', 'dcache_port'] + physmem_port = Port("Physical Memory Port") + _mem_ports = ['icache_port', 'dcache_port', 'physmem_port'] |