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authorNathan Binkert <nate@binkert.org>2009-04-08 22:21:27 -0700
committerNathan Binkert <nate@binkert.org>2009-04-08 22:21:27 -0700
commite0de2c34433be76eac7798e58e1ae02f5bffb732 (patch)
tree120f809cf3feb35e6b42e83a9896b8ae673c5445 /src/cpu/simple/atomic.cc
parent7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60 (diff)
downloadgem5-e0de2c34433be76eac7798e58e1ae02f5bffb732.tar.xz
tlb: More fixing of unified TLB
Diffstat (limited to 'src/cpu/simple/atomic.cc')
-rw-r--r--src/cpu/simple/atomic.cc7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index b5e65265a..601111588 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -314,7 +314,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
req->setVirt(0, addr, dataSize, flags, thread->readPC());
// translate to physical address
- Fault fault = thread->dtb->translateAtomic(req, tc, false);
+ Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
// Now do the access.
if (fault == NoFault) {
@@ -452,7 +452,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
req->setVirt(0, addr, dataSize, flags, thread->readPC());
// translate to physical address
- Fault fault = thread->dtb->translateAtomic(req, tc, true);
+ Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
// Now do the access.
if (fault == NoFault) {
@@ -609,7 +609,8 @@ AtomicSimpleCPU::tick()
bool fromRom = isRomMicroPC(thread->readMicroPC());
if (!fromRom && !curMacroStaticInst) {
setupFetchRequest(&ifetch_req);
- fault = thread->itb->translateAtomic(&ifetch_req, tc, false, true);
+ fault = thread->itb->translateAtomic(&ifetch_req, tc,
+ BaseTLB::Execute);
}
if (fault == NoFault) {