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| author | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
|---|---|---|
| committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
| commit | 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch) | |
| tree | 040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/cpu/simple/base.cc | |
| parent | 552622184752dc798bc81f9b0b395db68aee9511 (diff) | |
| download | gem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz | |
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Diffstat (limited to 'src/cpu/simple/base.cc')
| -rw-r--r-- | src/cpu/simple/base.cc | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 012a49253..078f490e8 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 2010-2012 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * * The license below extends only to copyright in the software and shall @@ -211,6 +212,18 @@ BaseSimpleCPU::regStats() .desc("number of times the floating registers were written") ; + numCCRegReads + .name(name() + ".num_cc_register_reads") + .desc("number of times the CC registers were read") + .flags(nozero) + ; + + numCCRegWrites + .name(name() + ".num_cc_register_writes") + .desc("number of times the CC registers were written") + .flags(nozero) + ; + numMemRefs .name(name()+".num_mem_refs") .desc("number of memory refs") |